CS302 MID Term Paper 2010 - 1

MIDTERM EXAMINATION
Spring 2010
CS302- Digital Logic Design (Session - 6)

Time: 60 min
M - 38

CS302- Digital Logic Design - Q.No. 1 ( M - 1 )
The maximum number that can be represented using unsigned octal system is _______

► 1

► 7

► 9

► 16

CS302- Digital Logic Design - Q.No. 2 ( M - 1 )

If we add “723” and “134” by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be ________

► 0

► 1

► 2

► 3


CS302- Digital Logic Design - Q.No. 3 ( M - 1 )

The diagram given below represents __________



► Demorgans law

► Associative law

► Product of sum form

► Sum of product form


CS302- Digital Logic Design - Q.No. 4 ( M - 1 )

The range of Excess-8 code is from ______ to ______

► +7 to -8

► +8 to -7

► +9 to -8

► -9 to +8

CS302- Digital Logic Design - Q.No. 5 ( M - 1 )

A non-standard POS is converted into a standard POS by using the rule _____


► .

►

►

► A+B = B+A

CS302- Digital Logic Design - Q.No. 6 ( M - 1 ) 

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12

► 16


CS302- Digital Logic Design - Q.No. 7 ( M - 1 )

The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?


► A > B = 1, A < B = 0, A < B = 1

► A > B = 0, A < B = 1, A = B = 0

► A > B = 1, A < B = 0, A = B = 0

► A > B = 0, A < B = 1, A = B = 1



CS302- Digital Logic Design - Q.No. 8 ( M - 1 )

A particular Full Adder has

► 3 inputs and 2 output

► 3 inputs and 3 output

► 2 inputs and 3 output

► 2 inputs and 2 output



CS302- Digital Logic Design - Q.No. 9 ( M - 1 )

. The function to be performed by the processor is selected by set of inputs known as ________

► Function Select Inputs

► MicroOperation selectors

► OPCODE Selectors

► None of given option



CS302- Digital Logic Design - Q.No. 10 ( M - 1 )
For a 3-to-8 decoder how many 2-to-4 decoders will be required?


► 2

► 1

► 3

► 4



CS302- Digital Logic Design - Q.No. 11 ( M - 1 )

GAL is an acronym for ________.


► Giant Array Logic

► General Array Logic

► Generic Array Logic

► Generic Analysis Logic



CS302- Digital Logic Design - Q.No. 12 ( M - 1 )

The Quad Multiplexer has _____ outputs

► 4

► 8

► 12

► 16



CS302- Digital Logic Design - Q.No. 13 ( M - 1 )
A.(B.C) = (A.B).C is an expression of __________

► Demorgan’s Law

► Distributive Law

► Commutative Law

► Associative Law



CS302- Digital Logic Design - Q.No. 14 ( M - 1 )

2's complement of any binary number can be calculated by

► adding 1's complement twice

► adding 1 to 1's complement

► subtracting 1 from 1's complement.

► calculating 1's complement and inverting Most significant bit



CS302- Digital Logic Design - Q.No. 15 ( M - 1 )

The binary value “1010110” is equivalent to decimal __________

► 86

► 87

► 88

► 89



CS302- Digital Logic Design - Q.No. 16 ( M - 1 )

Tri-State Buffer is basically a/an _________ gate.

► AND

► OR

► NOT

► XOR


CS302- Digital Logic Design - Q.No. 17 ( M - 2 )

For what values of A, B, C and D, value of the expression given below will be logic 1. Explain at least one combination.



CS302- Digital Logic Design - Q.No. 18 ( M - 2 )

provide some of the inputs for which the adjacent 1s detector circuit have active high output?



CS302- Digital Logic Design - Q.No. 19 ( M - 2 )

. Draw the Truth-Table of NOR based S-R Latch


CS302- Digital Logic Design - Q.No. 20 ( M - 3 )

For a two bit comparator circuit specify the inputs for which A > B


CS302- Digital Logic Design - Q.No. 21 ( M - 3 )

Draw the circuit diagram of NOR based S-R Latch ?


CS302- Digital Logic Design - Q.No. 22 ( M - 5 )

One of the ABEL entry methods uses logic equations; explain it with at least a single example.


CS302- Digital Logic Design - Q.No. 23 ( M - 5 )

Explain Carry propagation in Parralel binary adder?